The development of components based systems consists on assembling a set of basic units, where each unit covers a part of system requirements. This approach allows the reduction of development cost. However, the assembling operation requires the adoption of a complete and less costly verification approach. In this paper, we propose a formal approach to verify the compatibility of SysML blocks where the goal is to study the possibility of their composition. Essentially, a SysML specification of a system consists of representing its structure in a form of a blocks set in interaction, this interaction can be modelled with models which exposes a level of hierarchy. Thus, our approach aims to benefit from the hierarchy that we find in SysML models and in automata to alleviate the verification of SyML blocks compatibility.